The present invention relates to solid state memory devices, and more specifically, to multi-bit spin-momentum transfer magnetoresistive random access memory devices that include a single magnetic-tunnel-junction stack.
An attribute of solid state memory technology is the size or area occupied by each bit of a given solid state device (e.g., a transistor), which is closely tied to cost per bit. A goal of solid state memory technology is to store more than one bit of information per memory cell, effectively multiplying the density with little additional cost. Spin-momentum-transfer (SMT) magnetoresistive random access memory (MRAM) is a non-volatile solid state memory device that uses the direction of magnetic moment in the free layer to store digital information, and use the SMT effect to change the magnetic moment direction and write digital data. The magnetic element at the center of this type of MRAM cell is the magnetic-tunnel-junction (MTJ). An MTJ has two ferromagnetic elements separated by an ultra-thin insulator. Conventionally, multi-bit cell designs for SMT-MRAM devices rely on stacking two or more different MTJ devices vertically. These vertically stacked MTJ devices must have carefully tuned properties so that the total resistance of the two MTJ in series results in four well-separated levels, and that the threshold for writing each one of the devices are well separated as well. Since both the resistance and the write threshold for MTJ are related to the area of tunnel barrier, the sidewall profile of the stacked MTJ devices is a parameter that must be carefully selected. This sensitivity results in small process window, lower yield or slower performance.